Many years ago I got my private pilot’s license, and there is nothing that I love better than being behind the controls of a small plane. When the plane leaps off the runway and into the sky, the feeling is exhilarating. Then, after executing a perfectly smooth landing, there is a sense of triumphant success. In addition to the pure joy of flying, there are also many ideas and lessons that I have taken from my time in the air.
One of these has been to learn to rely on a PCB design rule checklist.I have read many small plane accident reports, and one theme that runs through many of them is that a crash is often due to something important that was forgotten. That is the whole reason for a PCB design rule checklist: to help you remember those things that are essential for your success. I have also found that using a checklist while designing a printed circuit board (PCB) helps me to remember important steps, especially as I am preparing the design for layout.Having a pre-layout design checklist will help you to organize all of your information, even if it isn’t all immediately available to you. Knowing exactly what the purpose and parameters of the Printed Circuit are supposed to be before you start layout can help avoid costly re-designs. You can record the information that you have and what you still need right on your checklist. By knowing the details of your checklist, you can make sure that your design takes flight instead of crashing.PCB Pre-Layout Design Checklist: Is the Schematic Ready?One of the first things that you will want to do in your pre-layout checklist is to make sure that the schematic is ready to go. This does not mean that the schematic has to be 100% completed.
Often a schematic is only partially completed when the design goes into layout. The important thing in making sure that the schematic is ready for layout is to confirm that it is in an acceptable state to proceed.One issue that can cause problems in layout is if undesired circuitry has been left in the schematic. This can happen if portions of the schematic were copied from another design, or if undesired circuitry didn’t get deleted. These extraneous portions of the circuit board can unintentionally alter nets or components. I have seen layouts that call for an extra because an undesired global power symbol was accidentally left in the schematic.
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I have also seen excess being placed because undesired gates had been left stranded in the schematic.One of the ways to avoid this is to insist that the schematic goes through a pre-layout review. These reviews get other people with fresh eyes looking at the design.
Often others can spot simple issues like this that the main has overlooked. Once the review is finished, you can cross this item off of your checklist.To successfully get your PCB design from schematic to layout, use a pre-layout checklistDo You Have All of the PCB Information That You Will Need for Layout?There is some basic design information that you should have before you start layout. Having this information on the checklist is a great way to confirm that you have it, or will serve as a way to document it if it is missing.
Here are some items that you will want to know:.Board specifications: You need to know the parameters for the board outline before you start. Changes after layout has started could significantly impact your design.Layer stackup: Your layout will be heavily influenced by the. Adding and removing layers during the layout is a major undertaking.Design technologies: Before you start you need to know what your goals are when designing a PCB board. Will this design include high-speed, RF, or other specific technologies?
Are there specific power layout requirements for this board? These questions need answers before you start so that you don’t have to go back later and re-do a lot of work.Being prepared before you start layout is the best guarantee to success in your PCB designIs Your Design Database Ready to Start Layout?I have seen lots of designers plunge into a layout when they actually weren’t ready to start yet. If you aren’t organized when you start the design, you may find yourself flying without an engine. For instance, if you’ve started a design with an incorrect component footprint, you may have to go back and re-design significant portions of the board to retrofit the correct footprint into the design. Here are some layout items to consider before you get started:.Footprint libraries: As I mentioned, an incorrect footprint could cause a lot of problems later on. You don’t have to have them all correct in order to start a design, but you do need to know which ones may be updated later. This way you can leave room for changes, or even wait on placing those components until they are correct.Board outline: As with the component footprints, you need to know if your board outline is finalized or not.
If it is going to change, you need to be prepared.Design rules and constraints: You need to setup as many design rules and constraints as possible before you start layout. This will keep you from having to go back later and re-design critical areas of the board to correct trace widths and clearances.With a completed checklist, you can begin your layout with confidence knowing exactly what it is that you have to work with., like, has place and route functionality that will work well with your PCB pre-layout design checklist. As you go through the list, you can easily see in both the schematic and the layout side-by-side what you have and what you still need in order to proceed with layout.Would you like to find out more about how Altium can help you to with PCB design? About the AuthorPCB Design Tools for Electronics Design and DFM. Information for EDA Leaders.
At Least One Ground Plane PresentEvery board must have at least one continuous ground plane to:. Provide a low-impedance power system. Make the connection of low-impedance vias to device GND pins very convenient.
Provides a path for return currents.All of these are very important in for keeping ground noise at a minimum, both on the board and in the devices. Dedicated Plane for VCCoIncluding an optional VCCo plane (continuous, dedicated, or semi-dedicated) greatly simplifies board layout. It increases the accessibility of routing connections to power pins and bypass capacitors and provides a low-impedance path for return currents. Every Signal Trace is Within One Signal Layer of a Continuous Reference PlaneEvery trace in the stackup should either be adjacent to a reference (power or ground) plane, or only separated from the closest reference plane by one signal layer.
This ensures that return currents always travel as near as possible to their corresponding trace. Adjacent signal layers should run in perpendicular directions so that vertical and horizontal layers alternate.This limits crosstalk between signal traces of adjacent layers. To maintain constant impedance from layer to layer, adjust the trace widths for each layer. See page 3 of for information on calculating the characteristic impedance of a PCB trace based on its dimensions, or use a field solver.
It is important to maintain continuity of the reference plane. Signal traces should never cross discontinuities (large hole, slot, or break) in their associated reference plane. High-frequency Capacitor Within 1 to 2 cm of Each VCC pinHigh-frequency bypass capacitors are the smallest capacitors in the bypassing network. There should be at least one high-frequency capacitor on every VCC/GND pair, mounted within 1 to 2 centimeters of the VCC pin it is bypassing. The best location for these capacitors is underneath the PCB, directly beneath the FPGA.Capacitor vias should never be shared.
Each capacitor requires at least 2 vias connections: one ground, and one Vcc. Vias should descend directly to the power and ground planes (Do not use traces to connect bypass capacitors to the power pins they service).The total capacitance of all high-frequency capacitors must be at least 25 times the equivalent switched capacitance ( C=P/(FV2) for VCCint, C=CLOAD.N for VCCio). For greater noise immunity, a factor of 50 or 100 should be used instead of 25. When one capacitor per VCC/GND pin is used, this calculation usually results in a range of 0.1µF to 0.01µF. Smaller values of 0.0047µF and 0.0033 µF should also be used.All high-frequency capacitors should be low ESR ceramic chips. Always use the smallest package for a given capacitor value.
See page 2 of for more information on choosing capacitor size and characteristics. See capacitor vendors' websites for specific information on capacitor characteristics. Mid-frequency Capacitors Within 8cm of VCC PinsMid-frequency bypass capacitors are low ESR, low inductance capacitors ranging from 4.7µF to 47µF. Tantalum capacitors are ideal; aluminum electrolytic capacitors may also be used.
Use at least one for every 3000 slices (two for V400 four for V1000, 7 for V2000E). Low-frequency Capacitors Anywhere on PCBLow-frequency bypass capacitors for board bypassing range from 47 µF to 4700 µF. For this function, any type of capacitor may be used anywhere on the board. Bypass Capacitor on Each Vref PinBecause of their high input impedance, Vref pins are succeptible to noise coupled in from surrounding signals.
Every Vref pin needs a local bypass capacitor ranging from 0.01µF to 0.1µF. Noise from the power supply is not a concern, so do not use inductors or ferrite beads here. Each Trace has Constant ImpedanceEvery signal trace should maintain the same impedance no matter where it goes. Signal traces may be of any practical impedance value (40 ohms to 100 ohms is common). The same design may have signal traces with a variety of different impedance values. However, a single trace should not change impedance values over its length.
For example, if a trace starts on one board layer and switches to another layer, the designer must ensure that the trace on the second layer has the same impedance as the first. If the layers are different distances from their respective reference planes, the widths of the signal traces should be adjusted accordingly.
In general, if the distance to the reference plane is increased, the trace width must also be increased in order to maintain the same impedance. Traces Longer Than Tr/6 have been SimulatedThe ratio of signal rise/fall time to trace length can determine whether or not transmission-line effects will occur. In general, long traces with fast rise/fall times exhibit transmission-line effects. If the time it takes a signal to propagate down the length of the trace is more than 1/6 of the signal rise/fall time, transmission-line effects are likely, and the signal path must be simulated. This can be perfomed in an IBIS or SPICE simulator. For more information on transmission-line effects and simulation, see the text references at the end of this document.
If Ringing or Overshoot is Observed, Add Termination or Change IO StandardA simulated transmission line that exhibits ringing or overshoot indicates an unacceptable amount of signal reflection. Signal reflection occurrs when a signal wave encounters an impedance discontinuity. To repair the ringing or overshoot, you must eliminate the impedance discontinuity in one of three ways:. Add resistive termination to the PCB (in series or parallel). Change the SelectIO standard to one with a lower current drive. Use XCITE DCI (in Virtex-II).For further information on termination, see. Extra Attention has been Paid to Clock Signals (GCLK, CCLK, TCK etc)Clock signals require special attention for two reasons.
First, it is critical that their timing not be marginalized by noise - this can lead to false clocking of data. Second, clock signals often run at a higher frequency than data; they can be more troublesome as noise sources. Clock traces and their drivers should ALWAYS be carefully simulated prior to PCB fabrication. Long, Closely-spaced Parallel Traces have been Analyzed for CrosstalkPay attention to any traces running in parallel for long distances.
Simulate any suspicious traces using a PCB crosstalk simulation tool to determine if they will cause problems. If you confirm crosstalk as a problem, manage it by separating the traces or decreasing their distance from the associated reference plane (decrease dielectric thickness). Total FPGA Power Estimated with Power Estimator or XPowerThe or XPower should be used to determine the approximate power the FPGA will require. The Power Estimator requires design data generated by MAP (CLB utilization, Flops, IO standard, BlockRAM usage). XPower is part of the design flow.
These tools provide a guideline for power supply requirements and are essential for thermal planning. Power Supply Satisfies POR Monotonicity and Ramp Rate RequirementsThe power supplies should rise from less than 0.1 Vdc to the minimum DC operating condition voltage level in less than 50 milliseconds, and not faster than 1 millisecond. The rise should not be inhibited by a current trip, or current foldback. Current limit behavior is acceptable based on the 'Power-On Ramp Up Current Requirement' specification from the data sheet.
The voltage rise vs. Time should be roughly monotonic. Avoid dwelling at a voltage, or having a 'plateau', even if it is acceptable power supply behavior. If the voltage increases beyond the minimum operating voltage and then drops below it, you will experience incorrect power behavior.
If the power supply voltage falls below the absolute minimum operating voltage when the device is off, it should not rise immediately back to the nominal operating voltage when turned on without first discharging to below 0.1 Vdc. You may need a resistor to bleed off the filter and bypass capacitor charges to meet this condition. Power Supply Satisfies POR Minimum Current RequirementAside from meeting the dynamic power requirements determined by the, the power supply must also be able to supply the minimum specified startup current specified in the datasheet.
Die Temperature Predicted by TJ = TA + P.QJA is Less than Max AllowableDetermine the die temperature using the power figure derived from the Power Estimator, information about the device package, and the maximum ambient temperature in the operating environment. If it is higher than the maximum allowable temperature for the device temperature grade (C = Commercial: 0°C - 80°C, I = Industrial: -40°C - 100°C), the design must change (lower ambient temperature, add heatsink, change package, reduce clock frequency or reduce device utilization). Further information on thermal planning and management is located on page 1 of.